The invention relates generally to the field of electronic packaging, and more particularly to interconnects for electronic packaging and methods of making the same.
Typically, in electronic packaging, bus plating is employed to form interconnects. As will be appreciated, in bus plating, a conductive metal, such as copper, is deposited on a substrate or a board. Subsequently, the conductive layer is patterned to form a series of electrical traces that may include a series of conductive busses across the surface of the substrate. These busses are connected to a power source via a common bus and are used to form electrical connections from the power source to the traces. Subsequent to forming the busses, a patterned mask is formed over certain portions of the traces, while leaving other portions exposed. The contact pads are then formed on the exposed portions of the electrical traces.
As will be appreciated, during formation of traces by patterning the conductive layer, the conductive layer is exposed to the ambient environment and is highly susceptible to oxidization, which generally affects the adhesion of contact pads on the surface. Disadvantageously, poor adhesion between the conductive layer and the contact pads may affect the performance of the packaging in an undesirable manner. For example, poor adhesion may lead to increased resistance between the conductive layer and the contact pads and therefore may result in heating of the electronic packaging. This problem is compounded by recent trends to reduce the size of electronic devices while increasing the density per unit area, thereby increasing the interconnect density on the electronic packages. As a result, the performance of the device is increasingly impacted by limitations in interconnect technology and packaging of the chips used to fabricate the devices.
Accordingly, there is a need to provide improved interconnects for use in electronic packaging.